área de pesquisa
- Analytical logical effort formulation for local sizing
- Consumo em Portas Lógicas CMOS e Estudo do Componente Dinâmico de Curto-Circuito
- Design and Evaluation of Logic Gates Based on IG-FinFET
- Ernesto Cristopher Villegas Castillo
- KL-cut based remapping
- MCML Gate Design Methodology and the Tradeoffs Between MCML and CMOS Applications
- Paulo Henrique da Cunha Pedrosa
- Roberto Chura Chambi
- Thiago Wellington Joazeiro de Almeida