área de pesquisa
- A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal
- A Two-Level Approximate Logic Synthesis Method based on Insertion and Removal of Cubes
- Aging Aware Design Techniques and CMOS Gate Degradation Estimatives
- Analytical Delay Model for Static CMOS Gates
- Analytical logical effort formulation for local sizing
- Applications of Functional Composition for CMOS and Emerging Technologies
- Automatic Generation and Evaluation of Transistor Networks in Different Logic Styles
- CMOS digital integrated circuit design faced to NBTI and other nanometric effects
- Consumo em Portas Lógicas CMOS e Estudo do Componente Dinâmico de Curto-Circuito
- Design and Evaluation of Logic Gates Based on IG-FinFET
- Evaluation of using MIGFET devices in digital integrated circuit design
- Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation
- Functional Composition Paradigm and Applications
- Geração e Avaliação de Bibliotecas de Portas Lógicas CMOS
- Integração e Interoperabilidade de Ferramentas de CAD para Microeletrônica
- KL-cut based remapping
- KL-cuts : a new approach for logic synthesis targeting multiple output blocks
- Leakage Current Modeling in Sub-micrometer CMOS Complex Gates
- Logic Synthesis for Emerging Technologies
- Logic synthesis for sequential material implication logic based on resistance switching devices
- Metodologia para avaliação do impacto de efeitos de envelhecimento em flip-flops
- Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition
- On-silicon testbench for validation of soft logic cell libraries
- Parallel algorithms for scalable logic synthesis & verification
- Read Polarity Once Functions
- REINALDO ALVARENGA BERGAMASCHI
- Renato Perez Ribas
- SAT-Based Environment for Logical Capacity Evaluation of Via-Configurable Block Templates
- Synthesis of Threshold Logic Based Circuits
- Threshold Logic Technology Mapping for Emerging Technologies
- Two-Level and Multilevel Approximate Logic Synthesis